Release Note for Little Bay System Management Controller (SMC) CPLD


Revision History
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Little Bay System Management Controller CPLD Version :0.30
Copyright  2011, Intel Corporation and/or its suppliers and licensors. All rights reserved.
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Changes:


REVISION			 DESCRIPTION
0.22				Initial external release for Little Bay Fab A1 build with Tunnel Creek A0 Stepping

0.26				For Little Bay Fab D boards with B0 silicon. Won't work on earlier fabs.
				    - TOP.V line 203. THERMTRIP_3P3_N is valid only in M1,M5 state.
					  - VID_DEMUX.V line 53. VNN changes during M5.
						- THERMTRIP# assertion will shutdown system.
						- TOP.V line 205. THERMTRIP# LED clears with power button pressed as well.
						- PWRMGT.V L689. Added THERMTRIP# assertion for catastrophic shutdown.
						- PWRMGT.V L184. KBD_RST_N will trigger a warm reset. 			
						- Added KBD_RST_N pin to K3.
						- Removed HPLL_ENABLE fix.
						- Removed HIGHZ_N circuit.
						- V1P05_S and VNN_S ramps together to fix reverse polarity on PWRMODE. v_seqcr.v.
						- S3 wake sequence is corrected to match EDS. The power button (wake event) will assert WAKE_N to Tunnel Creek and 
						  Tuneel Creek will deassert SLPRDY then CPLD goes to S0.
						- External button warm reset corrected to match EDS. It wasn't working on Tunnel Creek A0 stepping, so a workaround was used for 
						  Tunnel Creek A0 stepping. In B0 stepping, the workaround is removed. Now it waits for RSTRDY# and SLPMODE from Tunnel 
						  Creek before it comes out of warm reset. Correction made on WARM_RESET_EXIT_1 state.
						- Checked Windows Restart, Standby, Shutdown, button reset, button power down, ITP halt. All functional.
				    - Now there is only one cold boot flow. ITP will have to do soft reset to break @ reset.
						- Removed the JTAG I/Os because HPLL_ENABLE fix is not required in Tunnel Creek B0 stepping
						- Checksum = 0030F055
				
0.28			 - PWROK is pulsed 10x during cold boot to work around a silicon issue.
					 - CB_WAKE_N is an open drain signal.
					 - Removed HIGHZ_N pin.
					 - Fixed bug on CPLD code that causes VNN to NOT latch VIDs correctly and only output the default voltage, which is 0.90V.
					 - Checksum = 0030030B
					 
0.30  		- Support Little Bay Fab D board with B0 silicon and Little Bay Fab E board with B1 silicon
					-	Added filter to slprdy_n, rstrdy_n & slpmode signals to mitigate metastability issue
					- Modified EC state machine to implement Gray Encoding to mitigate metastability issue
					- RSTWARN driven to 0 during S5 to fix back drive issue on 3.3V_S
					- Removed weak pullups for slprdy_n, rstrdy_n & slpmode signals to fix back drive issue on 3.3V_S
					- Added weak pull up on OVR_ALL_VID_N to fix dynamic voltage stepping
					- Added timing constraints to the design by adding a SMC.sdc file required at sysnthesis and Place/Route to fix 34 synthesis 
						warnings & 3 critical synthesis warnings including timing violations.
          - Added timing constraint file SMC.sdc. This file must be used during sysnthesis & Place and route.
					- Added debouncer circuit on RESET and POWER button signals to mitigate ringing caused by inductive kick during button depression & release
         	- Added additional stage of retiming on slp_s3_n and slp_s5_n to mitigate metastability issue
          - Synchronised s3_pwrgd and s5_pwrgd to mitigate metastability issue
          - Removed debug pins - OVL_TCK, OVL_TMS, OVL_TDI, OVL_TRST_N, XDP_PRSNT_N to remove synthesis warning
          - Added special Warm Reset to support TNC B0/B1 feature that ensure cDMI training completes.
					- Checksum = 002EF618




		*Due to licensing constraint, the following megafunction has been removed from this release and will be needed to work with this release.
		The megafunction can be obtained from Altera development tool.
		// megafunction wizard: %MAX II oscillator%
		// GENERATION: STANDARD
		// VERSION: WM1.0
		// MODULE: altufm_osc 
						
					 
 
